1. Field of the Invention
The present invention relates generally to integrated circuit (IC) design, and more particularly to an electro-static discharge (ESD) protection circuit having a resistive/capacitive (RC) triggered ESD clamp capable of extended clamp-on times.
2. Background of the Invention
Semiconductor devices in ICs are known to be susceptible to damage from an ESD event. An ESD event may cause extremely high currents to flow through CMOS devices. As a result, the device junctions, gate oxides, and other adjacent structures may be permanently damaged.
Because of aggressive scaling of IC dimensions in advanced sub-micron technologies, protecting ICs from damage during ESD events is receiving a renewed focus. As IC technology scales or becomes smaller, device channel lengths and snapback voltage are reduced. When the drain to source voltage reaches certain levels, a device may enter the destructive snapback region. As a result, scaling of ICs increases the susceptibility of the IC devices to damage from ESD events. At the same time, scaled ICs are required to maintain the same level of ESD robustness as prior generations of IC technologies.
In the prior art, standard RC-triggered ESD clamps have been used for providing an ESD discharge path between power supplies and ground. During a typical IC″s power-up operation, it is desired that the IC″s ESD clamp(s) remain off. In order for this to occur, the ESD clamp″s RC network needs to charge at the same rate as the IC″s power-up ramp. That is, the RC network requires a small RC time constant (i.e., hundreds of nanoseconds to tens of microseconds) relative to the IC″s power-up ramp (i.e., typically hundreds of microseconds to tens of milliseconds).
However, during an ESD event, a current spike with a fast rise time of less than 10 ns may occur. During the ESD event, it is desired that the ESD clamp turn on and remain on during the high current portion of the ESD event, i.e., 500 ns or more. As a result, an RC time constant of approximately 500 ns or more is required depending on the level of ESD protection required. For example, for an IC power-up ramp rate in the tens of milliseconds and an ESD robustness target of 3 kV, an RC time constant of 500 ns is preferred.
Determination of the proper RC time constant becomes more difficult as the rise time of powering up an IC, i.e., 500 ns to tens of micro seconds, approaches the rise time of an ESD event, i.e., 10 ns. If the RC time constant is too large, the ESD clamp works well during the ESD event but allows too much leakage through the clamp(s) during power-up. Clamp leakage slows the IC power-up and may have adverse effects on “power on reset” circuitry possibly causing logic to initialize to the wrong state. Conversely, if the RC time constant is too small, there is little power-up leakage but the ESD clamp may shut off too soon during an ESD event potentially resulting in damage to the IC devices.
As illustrated in FIG. 1, one prior art circuit 2 employs a “diode connected” NFET as a resistor to the capacitance of the IC″s ESD clamp circuitry. Such a design typically allows too much clamp leakage because the PFET of the first inverter initially conducts more current than the diode connected NFET. As a result, the RC network charges too slowly and the IC power-up is slowed.
As illustrated in FIG. 2, in a second prior art circuit 4, a diode connected NFET is placed between the power rail and the source of the first PFET in the IC″s ESD clamp circuitry. In such a design, the first inverter in the ESD clamp circuit initially charges high slower than the output of the second inverter. As a result, the clamp may remain off in the initial stages of an ESD event thereby providing no protection to the IC. In addition, in such a design, since the switch point of the first inverter is reduced by the diode connected NFET, the node leading to the first inverter does not have to charge as high to flip the output of the first inverter. Thus, the clamp may not stay on for an extended length of time.
A third prior art circuit (not shown) utilizes a large resistance, i.e., 1 M ohm, between the output of the first inverter and ground. Although effective, such a design is difficult to use in increasing scaled IC designs because the large resistance requires a large amount of IC area.